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Integrated Circuit Systems, Inc.
ICS9250-18
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: BX, Appollo Pro 133 type of chip set. Output Features: * 3 - CPUs @2.5V, up to 166MHz. * 17 - SDRAM @ 3.3V, up to 166MHz. * 7 - PCI @3.3V * 2 - IOAPIC @ 2.5V * 1 - 48MHz, @3.3V fixed. * 1 - 24MHz @ 3.3V * 2 - REF @3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support power management: CPU, PCI, stop and Power down Mode form I2C programming. * Spread spectrum for EMI control ( 0.25% center spread) * Uses external 14.318MHz crystal Key Specifications: * CPU - CPU: <175ps * CPU - PCI: 1 - 4ns * PCI - PCI: <500ps * SDRAM - SDRAM: <250ps
Pin Configuration
VDDREF *FS2/REF1 *PCI_STOP#/REF0 GND X1 X2 VDDPCI *MODE/PCICLK_F *FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI PCICLK5 BUFFERIN SDRAM11 SDRAM10 VDDSDR SDRAM9 SDRAM8 GND SDRAM15 SDRAM14 GND SDATA 2 IC SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDLIOAPIC IOAPIC0 IOAPIC_F GND CPUCLK_F CPUCLK1 VDDLCPU CPUCLK2 GND CPU_STOP# SDRAM_F VDDSDR SDRAM0 SDRAM1 GND SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 GND SDRAM12 SDRAM13 VDD48 24MHz/FS0* 1 48MHz/FSI*
{
56-Pin SSOP Block Diagram
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs ** Internal Pull-down resistor of 240K to GND on indicated inputs. 1. This output is double strength.
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 80.00 75.00 83.31 66.9 103.00 112.01 68.01 100.7 120.00 114.99 109.99 105.00 140.00 150.00 124.00 133.9 PCICLK (MHz) 40.00 37.50 41.65 33.45 34.33 37.34 34.01 33.57 40.00 38.33 36.66 35.00 35.00 37.50 31.00 33.25
9250-18 Rev B 9/23/99 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9250-18
ICS9250-18
Pin Configuration
PIN NUMBER 2 P I N NA M E REF1 FS21 REF0 P C I _ S TO P # 1 TYPE OUT IN OUT IN PWR IN OUT OUT IN IN OUT OUT IN IN IN OUT IN OUT IN PWR DESCRIPTION 14.318 MHz reference clock output L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D P C I 14.318MHz reference clock output Halts PCICLK [5:1] at logic "0" level when low. (in mobile, MODE=0) Ground. 14.318MHz input. Has internal load cap, (nominal 33pF). Crystal output. Has internal load cap (33pF) and feedback resistor to X1 F r e e r u n n i n g B U S c l o c k n o t a f e c t e d b y P C I _ S TO P # Latched input for MODE select. Converts pin 3 to PCI_STOP# when low for power management. Latched frequency select input, pull-down F r e e r u n n i n g B U S c l o c k n o t a f e c t e d b y P C I _ S TO P # PCI Clock Outputs. Input for Buffers S e r i a l d a t a i n f o r s e r i a l c o n fi g p o r t . ( I 2 C ) Clock input for serial config port. (I2C) 24MHz clock output for Super I/O or FD. L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 4 . 48MHz clock output for USB, 2X strength. L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 2 . Nominal 3.3V power supply, see power groups for function.
3
4, 10, 23, 26, 34, 42, GND 48, 53 5 6 8 X1 X2 PCICLK_F MODE1 FS31 PCICLK0 PCICLK [5:1] BU F F E R I N SDATA SCLK 24MHz 30 FS01 29 1, 7, 15, 20, 31, 37, 45 24, 25, 32, 33, 18, 19, 21, 22, 35, 36, 38, 39, 40, 41, 43, 44 46 47 50, 56 55 51, 49 52 54 48MHz FS11 VDDPCI, VDDREF, VDDSDR, VDD48 SDRAM [15:0]
9 16, 14, 13, 12, 11 17 27 28
OUT
SDRAM clocks
SDRAM_F C P U _ S TO P # VDDLCPU, VDDLIOAPIC I OA P I C 0 CPUCLK [2:1] CPUCLK_F I OA P I C _ F
OUT IN PWR OUT OUT OUT OUT
Free running SDRAM clock Not affected by CPU_STOP# Halts CPUCLK [2:1], IOAPIC0, SDRAM [15:0] clocks at logic "0" level when low. CPU and IOAPIC clock buffer power supply, 2.5V nominal. IOAPIC clock output. (14.318 MHz) Poweredby VDDL1 CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz) Free running CPU output clock. Not affected ty the CPU_STOP#. Freerunning IOAPIC clock output. Not affected by the CPU_STOP# (14.31818 MHz) Powered by VDDL1
Notes: 1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9250-18
General Description
The ICS9250-18 is the single chip clock solution for Desktop/designs using BX, Appollo Pro 133 type of chip sets. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-18 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE (Latched Input) 0 1 Pin 3 PCI_STOP# (Input) REF0 (Output)
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ICS9250-18
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9250-18
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description CPUCLK PCICLK Bit2 Bit7 Bit6 Bit5 Bit4 MHz MHz 0 0 0 0 0 80.00 40.00 0 0 0 0 1 75.00 37.50 0 0 0 1 0 83.31 41.65 0 0 0 1 1 66.9 33.45 0 0 1 0 0 103.00 34.33 0 0 1 0 1 112.01 37.34 0 0 1 1 0 68.01 34.01 0 0 1 1 1 100.7 33.57 0 1 0 0 0 120.00 40.00 0 1 0 0 1 114.99 38.33 0 1 0 1 0 109.99 36.66 0 1 0 1 1 105.00 35.00 0 1 1 0 0 140.00 35.00 0 1 1 0 1 150.00 37.50 0 1 1 1 0 124.00 31.00 0 1 1 1 1 133.9 33.25 1 0 0 0 0 135.00 33.75 1 0 0 0 1 129.99 32.50 1 0 0 1 0 126.00 31.50 1 0 0 1 1 118.00 39.33 1 0 1 0 0 115.98 38.66 1 0 1 0 1 95.00 31.67 1 0 1 1 0 90.00 30.00 1 0 1 1 1 85.01 28.34 1 1 0 0 0 166.00 41.50 1 1 0 0 1 160.01 40.00 1 1 0 1 0 154.99 38.75 1 1 0 1 1 147.95 36.99 1 1 1 0 0 145.98 36.50 1 1 1 0 1 143.98 35.99 1 1 1 1 0 141.99 35.50 1 1 1 1 1 138.01 34.50 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0.25% (Center Spread) 0 - Running 1- Tristate all outputs
PWD
Bit 2,7, 6:4
XXXX Note1
Bit 3 Bit 1 Bit 0
0 1 0
Note 1. Default at Power-up will be for latched logic inputs to define frequency as displayed by Bit 3. Note: PWD = Power-Up Default
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ICS9250-18
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable) Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 46 49 51 52
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d SDRAM_F (Act/Inact) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK_F (Act/Inact)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 8 16 14 13 12 11 9
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d PCICLKF (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 29 30 33, 32, 25, 24 22, 21, 19, 18 39, 38, 36, 35 44, 43, 41, 40
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d 48MHz (Act/Inact) 24MHz (Act/Inact) SDRAM(12:15) (Act/Inact) SDRAM (8:11) (Act/Inact) SDRAM (4:7) (Act/Inact) SDRAM (0:3) (Act/Inact)
BIT PIN# PWD Bit 7 X Bit 6 1 Bit 5 1 Bit 4 X Bit 3 1 Bit 2 1 Bit 1 X Bit 0 1
DESCRIPTION Latched FS0# R e s e r ve d R e s e r ve d Latched FS1# R e s e r ve d R e s e r ve d Latched FS3# R e s e r ve d
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT PIN# PWD Bit 7 1 Bit 6 X Bit 5 54 1 Bit 4 55 1 Bit 3 1 Bit 2 1 Bit 1 2 1 Bit 0 3 1
DESCRIPTION R e s e r ve d Latched FS2# IOAPIC_F (Act/Inact) IOAPIC0 (Act/Inact) R e s e r ve d R e s e r ve d REF1 (Act/Inact) REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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6
ICS9250-18
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS925018 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
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7
ICS9250-18
Fig. 2a
Fig. 2b
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ICS9250-18
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9250-18. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
INTERNAL CPUCLK PCICLK (0:5) CPU_STOP# PCI_STOP# (High) IOAPIC0 SDRAM(0:15) CPUCLK (1:2) SDRAM_F CPUCLK_F
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9250-18. 3. IOAPIC output is stopped Glitch Free by CPUSTOP# going low. 4. PCI_STOP# is shown in a high (true) state. 5. All other clocks continue to run undisturbed.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9250-18. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9250-18 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the device. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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ICS9250-18
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND 0.5 V to V DD +0.5 V 0C to +70C 115C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2 VDD +0.3 V Input Low Voltage VIL GND -0.3 0.8 V A VIN = VDD 0.1 5 Input High Current IIH A Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 2.0 A Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 -100 Operating IDD3.3OP100 Select @ 100MHz; Sdram running 150 180 mA 200 Supply Current IDD3.3OP133 Select @ 133MHz; Sdram running n/a VDD = 3.3 V 12 14.318 16 MHz Input frequency Fi Input Capacitance1 CIN Logic Inputs 5 pF X1 & X2 pins 27 36 45 pF CINX Transition Time1 TTrans To 1st crossing of target Freq. 4 ms Settling Time1 TS From 1st crossing to 1% target Freq. 1 3 ms Clk Stabilization1 TStab From VDD = 3.3 V to 1% target Freq. 4 ms
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) CONDITIONS MIN PARAMETER SYMBOL Operating IDD2.5OP100 Select @ 100MHz; Max discrete cap loads IDD2.5OP133 Select @ 133MHz; Max discrete cap loads Supply Current
1
TYP 13 18
MAX 25 25
UNITS mA
Guaranteed by design, not 100% tested in production.
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10
ICS9250-18
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -12.0 mA 2 Output High Voltage VOH2B IOL = 12 mA Output Low Voltage VOL2B VOH = 1.7 V Output High Current IOH2B VOL = 0.7 V 19 Output Low Current IOL2B 1 VOL = 0.4 V, VOH = 2.0 V 0.4 Rise Time tr2B VOH = 2.0 V, VOL = 0.4 V 0.4 Fall Time tf2B1 Duty Cycle dt2B1 VT = 1.25 V 45 Skew group1: 1,2 and 1,F tsk2B1 VT = 1.25 V Skew group2: 2, F tsk2B1 VT = 1.25 V 1 VT = 1.25 V Jitter, One Sigma tj12B VT = 1.25 V -250 Jitter, Absolute tjabs2B1 1 VT = 1.25 V tjcyc-cyc2B Jitter, Cycle-to-cycle
1
TYP 2.3 0.2 -41 37 1 51 120 120 100 150
MAX UNITS V 0.4 V -19 mA mA 1.6 ns 1.6 ns 55.5 % 175 ps 254 ps 250 ps +250 ps 250 ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, 24MHz,REF0
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH5 IOH = -14 mA 2.4 Output Low Voltage VOL5 IOL = 6.0 mA Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V 10 Rise Time1 Fall Time
1 1
TYP 2.9 0.25 -42 18 1.1 1
MAX UNITS V 0.4 V -20 mA mA 2.5 2.5 55 250 800 ns ns % ps ps
tr5 tf5 dt5 tj1s5 tjabs5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, 24, 48MHz VT = 1.5 V, REF0 45
Duty Cycle Jitter1 Jitter1
1
50 100 250
Guaranteed by design, not 100% tested in production.
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ICS9250-18
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IOH = -18 mA 2.4 2.9 V Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA 0.2 0.4 V Output High Current IOH1 VOH = 2.0 V -58 -22 mA Output Low Current IOL1 VOL = 0.8 V 25 52 mA Rise Time1 Fall Time Skew
1 1 1 1
tr1 tf1 dt1 tsk1 tj11 tjabs1
VOL = 0.8 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 45
1.5 1.4 50 270 50 200
2.5 2.5 55 500 150 500
ns ns % ps ps ps
Duty Cycle
Jitter, One Sigma Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -28 mA IOL = 19 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 Rise Time Fall Time
1
MIN 2.4
33 0.5 0.5 45
TYP 2.8 0.34 -72 50
MAX UNITS V 0.4 V -42 mA mA 2 2.4 ns ns % ps ps ps ns ps ps
tr1 tf1 dt1
1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 04 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
1 1
Duty Cycle
50 130 180 3.5 50
56.3 250 250 410 4.4 150 250
Skew(Group1: F,0:4, 8:11) Skew(Group2: 5:7, 12:15) Skew(Group3: 0, 13) Skew(Buferin-Output) Jitter, One Sigma Jitter, Absolute1
1 1 1 1
tsk1 tsk1 tsk1 tsk1 tj11 tjabs1
1
-250
130
Guaranteed by design, not 100% tested in production.
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ICS9250-18
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH4B IOH = -12 mA 2 IOL = 12 mA Output Low Voltage VOL4B VOH = 1.7 V Output High Current IOH4B VOL = 0.7 V 19 Output Low Current IOL4B Rise Time1 Fall Time
1 1 1
TYP 2.2 0.3 -32 26 1.5 1 51 240 619
MAX UNITS V 0.4 V -19 mA mA 1.8 1.6 55 300 650 ns ns % ps ps
Tr4B Tf4B Dt4B Tj14B Tjabs4B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
0.4 0.4 45
Duty Cycle
Jitter, One Sigma Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
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ICS9250-18
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and ground traces as wide as the via pad for lower inductance.
Ferrite Bead VDD
C2 22F/20V Tantalum
C2 22F/20V Tantalum
Ferrite Bead VDD
1 2 3 4
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
C3
2.5V Power Route
Notes: 1) All clock outputs should have a series terminating resistor, and a 20pF capacitor to ground between the resistor and clock pin. Not shown in all places to improve readibility of diagram. 2) Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed.
C1
5 6 7 8 9 10 11
1 Clock Load
C1 2
C3
3.3V Power Route
12 13 14 15 16 17
3.3V Power Route
Ground
Ground
Component Values: C1 : Crystal load values determined by user C2 : 22F/20V/D case/Tantalum AVX TAJD226M020R C3 : 100pF ceramic capacitor C4 : 20pF capacitor FB = Fair-Rite products 2512066017X1 All unmarked capacitors are 0.01F ceramic
18 19 20 21 22 23 24 25 26
Connections to VDD:
27 28
= Routed Power = Ground Connection (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load
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ICS9250-18
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AD MIN. .720
D NOM. .725
N MAX. .730 56
SSOP Package
Ordering Information
ICS9250yF-18
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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15
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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